| General Parameters: |
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| Status: | Active |
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| Product Details: | PMI model number PTRAN-100M18G-SDLVA-2SFB-3UVPX-P4-MAH is a Transceiver covering 100 MHz to 18 GHz and fits into a 3U Open VPX form factor utilizing a high-speed VITA 67 connector. This unit up-converts a 100 MHz to 4 GHz transmit signal to the 2 GHz TO 18 GHz range. The unit also down-converts a 100 MHz to 18 GHz received signal to the 100 MHz to 4 GHz intermediate frequency range for analog to digital conversion. A receive filter bank incorporates a 2-way absorptive switch to select an input, along with two 6-way switches allowing one of six filter paths to be chosen. A second receive switching filter bank provides an additional five filter paths. Two filter banks are also used on the transmit path, with two six-way switches allowing one of six filter paths to be chosen in the first, and an additional five filter paths are included in the second. The unit is made to attach an FPGA card allowing for a total solution. |
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| Inputs: | J1, J4A, J4B, J9, J10 |
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| J1 Input: | RF Receive Input |
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| Frequency J1: | 100 MHz to 18.0 GHz |
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| SW CTL B (Trigger): | TTL 0: Limited RF CH SPST Switch On (Insertion Loss),
TTL 1: Limited RF CH SPST Switch Off (Isolation) |
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| V0 (Video Comparator Signal Amplitude): | LVTTL |
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| Video Comparator Delay: | 50 ns Typ |
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| Log Linearity: | ±1.75 dB (-40 °C to +85 °C) Max |
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| Power Level J1: | -80 to +10 dBm Typ |
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| Connector J1: | SMPM (M) |
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| Frequency J4A: | 100 MHz to 4.0 GHz |
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| Power Level J4A: | 0 dBm Typ |
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| Connector J4A: | VITA 67 |
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| Frequency J4B: | 100 MHz to 4.0 GHz |
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| Power Level J4B: | 0 dBm Typ |
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| Connector J4B: | VITA 67 |
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| Frequency J9: | 4.0 to 20.0 GHz |
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| Power Level J9: | +10 dBm Min, +20 dBm Typ |
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| Connector J9: | VITA 67 |
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| Frequency J10: | 4.0 to 20.0 GHz |
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| Power Level J10: | +10 dBm Min, +20 dBm Typ |
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| Connector J10: | VITA 67 |
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| Frequency J3A: | 100 MHz to 4.0 GHz |
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| Power Level J3A: | 0 dBm Typ for Limited SDLVA Channel |
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| Connector J3A: | VITA 67 |
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| Frequency J3B: | 100 MHz to 4.0 GHz |
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| Power Level J3B: | 0 dBm Typ for Limited SDLVA Channel |
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| Connector J3B: | VITA 67 |
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| Frequency J6: | 100 MHz to 18.0 GHz |
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| Power Level J6: | 0 to +10 dBm Typ |
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| Connector J6: | SMPM (M) |
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| Frequency J8: | 100 MHz to 18.0 GHz |
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| Power Level J8: | -40 to -30 dBm Output |
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| Connector J8: | SMPM (M) |
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| Connector J11: | SMA (F) (Cabled to UMC (F)) |
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| Connector J12: | Mezzanine Connector |
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| TTL 1 Logic '0': | Output to TX Filter Bank, RX-Backplane/Input (J1) |
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| TTL 1 Logic '1': | Output to RX Filter Bank, RX - Transceiver Input |
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| TTL 2 Logic '000': | Thru Channel |
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| TTL 2 Logic '001': | Channel 1 |
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| TTL 2 Logic '010': | Channel 2 |
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| TTL 2 Logic '011': | Channel 3 |
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| TTL 2 Logic '100': | Channel 4 |
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| TTL 2 Logic '101': | Channel 5 |
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| TTL 2 Logic '110': | Not Defined |
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| TTL 2 Logic '111': | Not Defined |
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| TTL 3 Logic '0': | Limited RF Output Channel |
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| TTL 3 Logic '1': | Linear RF Output Channel |
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| TTL 4 Logic '0': | Thru Channel |
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| TTL 4 Logic '1': | Down-Converted Channel |
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| TTL 5 Logic '0': | IF1 Output |
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| TTL 5 Logic '1': | IF2 Output |
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| TTL 6 Logic '0': | IF1 Input |
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| TTL 6 Logic '1': | IF2 Input |
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| TTL 7 Logic '0': | Thru Channel |
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| TTL 7 Logic '1': | Up-Converted Channel |
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| TTL 8 Logic '000': | Thru Channel |
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| TTL 8 Logic '001': | Channel 1 |
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| TTL 8 Logic '010': | Channel 2 |
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| TTL 8 Logic '011': | Channel 3 |
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| TTL 8 Logic '100': | Channel 4 |
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| TTL 8 Logic '101': | Channel 5 |
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| TTL 8 Logic '110': | Not Defined |
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| TTL 8 Logic '111': | Not Defined |
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| TTL 9 Logic '00000': | 0 dB Attenuation |
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| TTL 9 Logic '11111': | 31 dB Attenuation |
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| TTL10: | LO Select |
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| TTL10 Logic '00': | M1-LO1 M2-LO1 |
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| TTL10 Logic '01': | M1-LO1 M2-LO2 |
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| TTL10 Logic '10': | M1-LO2 M2-LO1 |
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| TTL10 Logic '11': | M1-LO2 M2-LO2 |
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| TTL11: | SDLVA Threshold Adjust |
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| TTL11 Logic '000000': | Lowest Threshold Level |
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| TTL11 Logic '111111': | Highest Threshold Level |
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| TTL12: | SDLVA CTL A (Enable) |
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| TTL12 Logic '0': | Internal Comparator Triggered SPST |
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| TTL12 Logic '1': | External Trigger Enable (SW CTL B) |
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| TTL13: | SDLVA CTL B (Trigger) |
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| TTL13 Logic '0': | Limited RF CH SPST Switch On (Insertion Loss) |
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| TTL13 Logic '1': | Limited RF CH SPST Switch Off (Isolation) |
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| TTL14: | Receive High Frequency Filter Select |
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| TTL14 Logic '000': | Thru Channel |
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| TTL14 Logic '001': | Channel 1 |
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| TTL14 Logic '010': | Channel 2 |
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| TTL14 Logic '011': | Channel 3 |
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| TTL14 Logic '100': | Channel 4 |
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| TTL14 Logic '101': | Not Defined |
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| TTL14 Logic '110': | Not Defined |
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| TTL14 Logic '111': | Not Defined |
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| TTL15: | Transmit High Frequency Filter Select |
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| TTL15 Logic '000': | Thru Channel |
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| TTL15 Logic '001': | Channel 1 |
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| TTL15 Logic '010': | Channel 2 |
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| TTL15 Logic '011': | Channel 3 |
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| TTL15 Logic '100': | Channel 4 |
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| TTL15 Logic '101': | Not Defined |
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| TTL15 Logic '110': | Not Defined |
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| TTL15 Logic '111': | Not Defined |
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